1. Field of the Invention
The present invention relates to a method for manufacturing a surface channel type P-channel MOS transistor.
2. Description of the Related Art
Generally, in a complementary MOS (CMOS) device, if a gate electrode of a P-channel MOS transistor as well as a gate electrode of an N-channel MOS transistor is of an N-type, the P-channel MOS transistor is of a buried channel type while the N-channel MOS transistor is of a surface channel type. In the buried channel type transistor, carriers flow deeper than an interface between a gate insulating layer and a semiconductor substrate (well). Therefore, the buried channel type transistor is not subjected to the surface scattering, and the mobility of carriers is relatively large. However, the burled channel type transistor is disadvantageous in terms of a punch through phenomenon, so that the channel length cannot be reduced.
In view of the foregoing, surface channel type P-channel MOS transistor are also adopted in CMOS devices.
In a first prior art method, after a gate electrode of boron-included polycrystalline silicon is formed on a gate silicon oxide layer, an annealing operation is carried out to activate impurity ions of source/drain regions. This will be explained later in detail.
In the first prior art method, however, during the above-mentioned annealing operation, the borons of the gate electrode easily penetrate the gate silicon oxide layer to reach the well (substrate). This is called a "boron penetration phenomenon". As a result, the threshold voltage of the transistor greatly fluctuates.
In a second prior art method, a gate insulating layer is made of silicon nitride. The penetration of borons in the gate electrode into the well (the substrate) can be suppressed by the gate silicon nitride layer. This will also be explained later in detail.
In the second prior art method, however, when the gate silicon nitride layer is very thin, it is impossible to control the thickness of the gate silicon nitride layer. It is also difficult to control the concentration of nitrogen in the nitrogen annealing operation, which makes the control of the nitrogen annealing operation complex, thus increasing the manufacturing cost.
In a third prior art method, nitrogen ions are implanted into a gate electrode (see S. Shimizu et al., "0.15 .mu.m CMOS Process for High Performance and Reliability", International Electron Device Meeting (IEDM), pp. 67-70, 1994). Thus, the penetration of borons in the gate electrode into the well (the substrate) can be suppressed by the nitrogen included in the gate electrode. This will also be explained later in detail.
In the third prior art method, however, the number of manufacturing steps is increased which increases the manufacturing cost. In addition, the high concentration of nitrogen in the gate electrode harms homogenous distribution of borons in the gate electrode.